Savin LD132c Manuale Utente Pagina 91

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i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 9
Freescale Semiconductor 91
3.7.11 Inter IC Communication (I
2
C) Timing
The I
2
C communication protocol consists of the following seven elements:
•Start
Data source/recipient
Data direction
Slave acknowledge
•Data
Data acknowledge
Stop
Figure 64 shows the timing of the I
2
C module. Table 69 and Table 70 describe the I
2
C module timing
parameters (IC1–IC6) shown in the figure.
Figure 64. I
2
C Module Timing Diagram
Table 69. I2C Module Timing Parameters: 3.0 V +/–0.30 V
ID Parameter
Standard Mode Fast Mode
Unit
Min. Max. Min. Max.
IC1 I2CLK cycle time 10 - 2.5 μs
IC2 Hold time (repeated) START condition 4.0 - 0.6 - μs
IC3 Set-up time for STOP condition 4.0 - 0.6 - μs
IC4 Data hold time 0
1
3.45
2
0
1
0.9
2
μs
IC5 HIGH Period of I2CLK Clock 4.0 - 0.6 - μs
IC6 LOW Period of the I2CLK Clock 4.7 - 1.3 - μs
IC7 Set-up time for a repeated START condition 4.7 - 0.6 - μs
IC8 Data set-up time 250 - 100
3
-ns
IC9 Bus free time between a STOP and START condition 4.7 - 1.3 - μs
IC10 Rise time of both I2DAT and I2CLK signals - 1000 20+0.1C
b
4
300 ns
IC11 Fall time of both I2DAT and I2CLK signals - 300 20+0.1C
b
4
300 ns
IC12 Capacitive load for each bus line (C
b
) - 400 - 400 pF
IC10
IC11
IC9
IC2
IC8
IC4
IC7
IC3
IC6
IC10
IC5
IC11
START
STOP START
START
I2DAT
I2CLK
IC1
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